SANTA CLARA, USA: NetLogic Microsystems Inc. announced the availability of the OP6100 family of digital front-end (DFE) processors which delivers 65MHz of occupied bandwidth, 145MHz of total bandwidth and 325MHz of pre-distortion bandwidth for next-generation 3G and 4G/LTE base stations, remote radio heads (RRUs) and distributed antenna systems (DAS).
This dramatic breakthrough represents over 220% increase in bandwidth over competing available merchant DFE solutions, and at a fraction of the cost and power of FPGA-based solutions. In addition, the innovative OP6100 DFE processor family supports multiple standards and multiple signals in the same wide bandwidth as well as full support over non-contiguous bands, and features NetLogic Microsystems’ Intelligent Self-Adaptive DFE technology.
The exponential growth in mobile data traffic in the next decade, coupled with global spectrum scarcity, are forcing service providers and operators worldwide to push the limits on capacity and throughput for their limited spectrum. This is in turn driving a need for next-generation base stations that can support dramatically wider bandwidth, significantly more signal channels and more protocols (2G/3G/4G) in each band.
By delivering the industry’s widest signal bandwidth, NetLogic Microsystems’ OP6100 DFE processor family enables the industry’s highest spectrum efficiency through the simultaneous processing of multiple signal channels per band, as well as the multi-protocol co-existence of 4G LTE, 3G and 2G standards.
This unique ability to support multiple signals and multiple protocols in a significantly wider bandwidth spectrum, coupled with the unique ability to span over non-contiguous bands, is enabling service providers to upgrade the performance and functionality of existing base stations without the time and costs associated with deploying new base stations or antennas.
Moreover, the OP6100 DFE processor family greatly improves the cost and power profiles of next-generation base stations by eliminating the need for costly and very power-hungry FPGA devices and conventional DFE solutions that are traditionally used to implement DFE functionality.