NUREMBERG, GERMANY: Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the latest member of their processor family: the high performance, high throughput FPS6 with integrated floating point. The FPS6 combines excellent integer performance, shared with the other members of the Cortus processor family, with a tightly integrated single precision floating point unit.
This processor IP is designed for integration into SoCs requiring high floating point performance: for example industrial control systems, motor control, power and energy applications. The FPS6 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3.
The Cortus FPS6 is a high performance, high throughput, 32-bit processor designed specifically for complex embedded systems. It features a high performance integer unit coupled with a pipelined floating point unit. It is the second member of the Cortus microcontroller IP core family to be released complementing the smaller, ultra low power APS3.The FPS6 instruction set is a superset of that of APS3 meaning that APS3 code can run on FPS6.
“We are delighted to offer a high throughput, scalable, floating point IP core for applications such as motor control or solar inverters” said Michael Chapman, CEO and president of Cortus. “FPS6’s modern RISC architecture ensures that the core can achieve a very high maximum clock frequency, for example 500 MHz at 65 nm”. In common with other Cortus processors, the FPS6 has a 5 to 7 stage integer pipeline and out-of-order completion ensure that most integer instructions (load and stores included) are executed in a single cycle.
The FPS6 delivers 30.5 MFlops for the Linpack benchmark (single precision at 333 MHz for 10 reps) providing a considerable advantage over an integer processor core. The FPS6 integer unit performance is 1.93 CoreMarks/MHz* and 1.67 DMIPS/MHz. For fixed point digital signal processing it is possible to add the APS DSP Co-processor to FPS6. The DSP co-processor works with 16-bit data and has a 20-bit accumulator.
The FPS6 has been designed to deliver scalable computing performance with symmetric multi-processing (SMP) such as dual- or quad-core configurations possible. For SMP configurations a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous FPS6/APS3 configurations. For example with a smart grid application, an APS3 might run a communications protocol stack while an FPS6 might run a power control application. Michael Chapman explains, “Software development for mixed processor sub-systems is straightforward as FPS6 and APS3 use the same toolchain”.
The modest silicon footprint of 0.26 mm2 in 130 nm (UMC) and 0.073 mm2 in 65 nm (TSMC) plus the freely available complete toolchain and IDE ensure a very low cost of ownership for FPS6 licensees. The easy software development programming in high level languages with simple debugging due to an integrated debugger and simulator enhance time to market and software reliability.
As a member of the Cortus family of processors it interfaces to all of Cortus’ peripherals via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The ecosystem around the FPS6 is rich and well developed, and it includes peripherals commonly used in embedded systems, bus bridges to ensure easy interfacing to other IP and system support and functions such as caches. A full development environment (for C and C++) is available, which can be customised and branded for final customer use. For the most demanding designs the FPS6 can be used in a multi-core configuration.